A1 - Hajduk, Zbigniew
N2 - The main goal of the thesis was development of new, effective methodology of the fuzzy Petri net transformation, which may be treated as formal desctription of a control algorithm of some process - into the digital circuit, assembled using FPGA matrix structures, both as synchronous and asynchronous systems. In the work are discussed: fuzzy Petri nets, asynchronous (self clocked) digital sequential circuits and their implementation using Field-Programmable Gate Arrays (FPGA), and the automation of digital systems described by Petri nets, together with their implementation using Verilog hardware description language. The following problems were solved:
N2 - 1. The method of how to transform a single place and the basic fragment of the fuzzy Petri net into the hardware module, as both synchronous, and asynchronous system was developed
N2 - 2. A new fuzzy RS flip-flop was introduced as synchronous, and a synchronous circuit, which has been used for the fuzzy Petri net implementation
N2 - 3. The method of the fuzzy Petri net synthesis which uses functional description in the Verilog language was developed
N2 - 4. The cost of the introduced net implementation was estimated
N2 - 5. The testing method of the hardware fuzzy Petri net was worked out, and microprocessor based testing device as a hardware and software was made
N2 - 6. A simple description format (specification) of the fuzzy Petri net structure was described, which is suitable for engineering applications
N2 - 7. A transformation process from textual description of the fuzzy Petri net into the complete Verilog code (as Intellectual Property Core), which describes the net behavior was automated (the computer program)
N2 - 8. The proposed methodology of synthesis was practically verified by assembling two control devices for laboratory plants
KW - systemy rozmyte
KW - sieci Petriego
KW - informatyka
KW - systemy cyfrowe
T1 - Sprzętowa implementacja rozmytych sieci Petriego jako układów sterowania